Abstract
Abstract: :
Purpose:Several devices have been designed for electrical stimulation for artificial vision applications. However, the majority of these devices do not offer precise control of amplitudes with arbitrary waveforms, simultaneous stimulation of multiple sites, and high channel counts. Our current device design consists of an embedded digital signal processor, FPGA, high resolution 32 channel digital to analog converter (DAC), high speed isolators, resistor programmable constant current sources with compliance voltages of +/–18volts and a 400Mbits/s IEEE1394 interface. The purpose of this study was to improve, test and characterize this high channel count, extra–corporeal retinal or cortical stimulator. Methods:Linear voltage to current converters were designed to output stimulus waveforms. A scaleable network of high speed DACs was designed with the capacity to support over 1000 non–multiplexed stimulating channels. A high performance DSP/FPGA embedded processing unit was used to update the 32 current sources at a rate of 19 Mbits per second. DSP and VHDL algorithms were optimized to process desired frequencies, amplitudes and phase delays. Two, sixteen–channel, high bandwidth analog multiplexers were coupled to high speed, fast settling–time, low–distortion FET–input amplifiers. This allowed real–time recording of the electrode compliance voltage for all electrodes, simultaneously. The current sources could be removed from the circuit, via DIP switches, allowing electrodes to be routed directly into FET input amplifiers for the purpose of recording neural physiologic signals via the analog multiplexers. External data acquisition systems were optically interfaced via photovoltaic isolation amplifiers. Advanced layout techniques were implemented to reduce EMI, crosstalk, distortion and noise. Results: At full–scale current, the maximum input frequency at which the output was distorted was 83.3kHz per channel at 5V/us slew rate. The power supplies used to attain these measurements were ±15 volts. DC Nickel Cadmium batteries significantly reduced the power noise issues. The optimized use of DSP/FPGA made it possible to achieve a maximum update rate of 31.25usec for all 32 channels using a 30MHz DAC clock. Conclusions:A high–channel count network–scalable stimulator has been designed and tested for high–speed interfacing to a real–time front–end image–processing system.
Keywords: retina • image processing • pattern vision